Joint Test Action Group (JTAG) is the common name for Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard test access port and boundary-scan architecture. JTAG was an industry group formed to develop a method for testing populated circuit boards after manufacture. JTAG was initially devised by electronic engineers for testing printed circuit boards using boundary scan and is still widely used for this application. Additionally, JTAG is used to control and observe on-chip instrumentation, program programmable logic, control test modes for manufacturing tests of the chip itself, and other similar purposes.
In many ICs today, all signal pins that connect to other devices on the board logic may be linked together in a set called a boundary scan chain. By using JTAG to manipulate the chip's external interface via inputs and outputs to other chips, it is possible to test for certain faults, caused mainly by manufacturing problems. By using JTAG to manipulate its internal interface (to on-chip registers), the IC or device logic may be tested.
In both cases (external and internal), this testing may be performed with the IC after it is mounted on the circuit card, and possibly while in a functioning system. When combined with scan, built-in self-test (BIST), and other test techniques, JTAG may enable a low overhead, embedded solution to testing an IC for certain static dynamic defects (shorts, opens, resistor and capacitor bridging and other defects). JTAG may also assist in diagnosing faults or testing for timing, temperature or other dynamic operational errors that may occur.
A JTAG interface is a special interface that may be added to an IC. Multiple chips on a printed circuit board (PCB) may have their JTAG lines daisy-chained together if specific conditions are met. A test probe may only have to connect to a single “JTAG port” to have access to all ICs on the chips on the PCB. For example, FIG. 1 shows an example of a circuit having a plurality of daisy-chained ICs 1051, 1052 and 1053. Each IC 105 has a test data in (TDI) port 110 and a test data out (TDO) port 115. A test clock (TCK) signal 120 may be provided to each of the ICs 105, and a test mode may be selected based on a test mode select (TMS) signal 125 provided to each of the ICs 105.
A manufacturer of an IC may desire to remotely communicate with one or more of the ICs it manufactures over various interfaces to perform various tests and troubleshooting procedures when necessary. However, it would be desired to have a mechanism in place to prevent an unauthorized party from monitoring (i.e., hacking into) the tests and troubleshooting procedures, which may provide the unauthorized party with sufficient information to reverse engineer the manufacturer's products. Further, the manufacturer may desire to have an authorized third party perform these tests and troubleshooting procedures on its behalf, without being able to obtain intimate knowledge of the interworkings and proprietary features of large portions of circuitry in the IC that may be used to support reverse engineering efforts.